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? semiconductor components industries, llc, 2013 october, 2013 ? rev. 2 1 publication order number: ncp81105/d ncp81105, ncp81105h drmos supporting, 1/2/3 phase power controller with svid interface for desktop and notebook vr12.5 & vr12.6 cpu applications the ncp81105 is a drmos supporting controller optimized for intel ? vr12.5 & vr12.6 compatible cpus. the controller combines true differential voltage sensing, differential inductor dcr current sensing, input voltage feed ? forward, and adaptive voltage positioning to provide accurately regulated power for both desktop and notebook cpu applications. the control system is based on dual ? edge pulse ? width modulation (pwm), to provide the fastest initial response to dynamic load events plus reduced system cost. the ncp81105 is compatible with drmos type power stages such as ncp5367, ncp5368, ncp5369 and ncp5338. the ncp81 105?s output can be configured to operate in single phase during light load operation ? improving overall system efficiency. a high performance operational error amplifier is provided to simplify compensation of the system. patented dynamic reference injection further simplifies loop compensation by eliminating the need to compromise between closed ? loop transient response and dynamic vid performance. patented total current summing provides highly accurate current monitoring for droop and digital current monitoring. features ? meets intel?s vr12.5 specifications ? implements vr12.6 ps4 state and svid reporting ? mixed voltage/current mode, dual edge modulation for fastest initial response to transient loading ? high impedance differential voltage amplifier ? high performance operational error amplifier ? high impedance total current sense amplifier ? true differential current sense amplifiers for balancing current in each phase ? digital soft start ramp ? dynamic reference injection ? accurate total summing current amplifier ? ?lossless? inductor dcr current sensing ? summed, thermally compensated inductor current sensing for adaptive voltage positioning (avp) ? 48 mv/ s fast output slew rate (ncp81105) ? 10 mv/ s fast output slew rate (ncp81105h) ? programmable slow slew rates as a fraction of fast slew rate ? reduced enable to first svid command latency ? phase ? to ? phase dynamic current balancing ? switching frequency range of 280 khz to 1.5 mhz ? starts up into pre ? charged loads while avoiding false ovp ? compatible with drmos power stages ? power ? saving phase shedding ? vin feed ? forward ramp slope compensation ? pin programming for internal svid parameters ? output over voltage protection (ovp) & under voltage protection (uvp) ? over current protection (ocp) ? power good output with internal delays ? this is a pb ? free device applications ? desktop and notebook microprocessors marking diagram http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 35 of this data sheet. ordering information qfn36 case 485cc a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package 36 1 ncp 81105 awlyywwg 1
ncp81105, ncp81105h http://onsemi.com 2 programming detection ncp81105 monitor amp dac ovp comparators max overcurrent overcurrent current current comparators uvlo & en error interface svid mux monitor thermal en 1 vcc 2 imax 16 vrhot# 3 sdio 4 alert# 5 sclk 6 int_sel 17 tsense 9 rosc 7 vrmp 29 vboot 30 vsp 36 csn1 19 csp1 18 _ + sense balance current amplifiers amp & logic state power pwm adc generators dac oscillator & ramp generators logic vr ready data registers i2 current dac ovp i1 i3 ocp forward 1.3v enable gate amp comp vsn vsp ps# pwm1 14 pwm3 13 pwm2 12 (vsp ? vsn) iout pwm2 1.3v _ _ + vr_rdy 8 vsn vsp pwm1 pwm3 buffer diffout 34 csn3 21 csp3 20 csn2 23 csp2 22 od# 10 smod 11 drvon 15 csref 24 cssum 25 cscomp 26 ilim 27 iout 28 fb 33 vsn 35 comp 32 enable ps# dac drvon vrmp ps# ps# vrmp cscomp csref dgain 31 iout feed ? scaling zero ovp enable enable ovp ocp ovp drvon ocp ovp drvon diff vrmp figure 1. block diagram
ncp81105, ncp81105h http://onsemi.com 3 figure 2. pin connections (top view) en od# smod pwm2 pwm3 pwm1 drvon imax int_sel csp1 vsp vsn diffout fb comp dgain vboot vrmp iout ilim 1 2 3 4 5 6 7 8 9 27 26 25 24 23 22 21 20 19 36 35 34 33 32 31 30 29 28 10 1 11 12 13 14 15 16 17 18 ncp81105 tab: ground vcc vrhot# sdio alert# sclk rosc vr_rdy tsense cscomp cssum csref csn2 csp2 csn3 csp3 csn1
ncp81105, ncp81105h http://onsemi.com 4 pin list and description pin no. symbol description 1 en logic input. logic high enables the ncp81105 and logic low disables it. 2 vcc power for the internal control circuits. a decoupling capacitor must be connected from this pin to ground. 3 vr_hot# open drain (logic level) output for over ? temperature reporting. low indicates high temp. 4 sdio bidirectional serial vid data interface. 5 alert# open drain serial vid alert# output. 6 sclk serial vid clock input. 7 rosc this pin outputs a constant current. a resistance from this pin to ground programs the switching fre- quency. 8 vr_rdy open drain output. high indicates that the ncp81105 is regulating the output. 9 tsense temperature sense input. 10 od# phase disabling output, tied to the enable, smod or zcd_en# pin of phases 2 and 3 drmos. except in ps0 mode, this output pulls low to disable the drmos if connected to an enable input. if connected to a drmos smod or zcd_en# input, both hs & ls fets are held off since pwm2 & pwm3 are also low. actively pulls high in ps0 mode. 11 smod phase 1 zero cross detection (zcd) disable output. in ps2 & ps3, smod pulls low when phase 1 inductor current is negative to perform (or allow the drmos zcd function to perform) diode emulation, and pulls high when phase 1 inductor current is positive. in ps0 & ps1, smod stays high to force the phase 1 drmos into continuous conduction. 12 pwm2 pwm output to phase 2 drmos 13 pwm3 pwm output to phase 3 drmos 14 pwm1 pwm output to phase 1 drmos 15 drvon enable output for drmos 16 imax during startup, a resistor from this pin to ground programs icc_max. 17 int_sel during startup, a resistor from this pin to ground programs the low frequency compensator pole of the ncp81105 voltage control feedback loop. 18 csp1 positive input to phase 1 current sense amplifier for balancing phase currents 19 csn1 negative input to phase 1 current sense amplifier 20 csp3 positive input to phase 3 current sense amplifier for balancing phase currents 21 csn3 negative input to phase 3 current sense amplifier 22 csp2 positive input to phase 2 current sense amplifier for balancing phase currents 23 csn2 negative input to phase 2 current balance sense amplifier 24 csref non ? inverting input for the total output current sense amplifier. also, the absolute ovp input. 25 cssum inverting input of total output current sense amplifier. 26 cscomp output of total output current sense amplifier. 27 ilim input to program the over ? current shutdown threshold. 28 iout total current monitor output. a resistor from this pin to ground calibrates svid output current reporting. 29 vrmp vdc applied to this pin provides feed ? forward compensation for the pulsewidth modulator. the current into this pin controls the slope of pwm ramp. a low voltage on this pin will inhibit ncp81105 startup. 30 vboot during startup, a resistor from this pin to ground programs the boot voltage 31 dgain during startup, a resistor from this pin to ground programs the scaling of the output droop with respect to the total output current signal produced between cscomp and csref. 32 comp output of the error amplifier. 33 fb error amplifier voltage feedback input. 34 diffout output of the differential remote sense amplifier. 35 vsn inverting input to the differential remote sense amplifier (vss sense). 36 vsp non ? inverting input to the differential remote sense amplifier (vcc sense). 37 gnd power supply return (qfn flag)
ncp81105, ncp81105h http://onsemi.com 5 ncp81105 phase vswh cout cb2 vin boot smod vcin pwm en phase vswh cb3 vin boot smod vcin pwm en phase vswh cb1 vin boot smod vcin pwm en pwm1 pwm2 pwm3 drvon smod od# drmos drmos drmos figure 3. three phase application diagram
ncp81105, ncp81105h http://onsemi.com 6 figure 4. three phase control circuit application vcc ilim csp2 diffout rosc fb place close to l1 sclk comp diffout place close to l1 vsp csn1 imon dgain vsense int_sel cscomp alert_vr 790khz switching frequency 95a maximum output current 114a current limit 1.5mohm loadline 1.7v boot voltage tsense csref cssum csn2 vr_rdy csp3 vsn sdio csp1 c156 68pf enable c80 22nf r78 43.2 c51 1nf r8 10.0 r48 100 c82 0.01uf c56 270pf r156 54.9 r18 17.4k c79 1uf r162 130 vr_hot c81 1nf r19 69.8k c85 22nf c57 10pf r161 1.0k r27 10.0k r43 4.75k r37 1.00k c61 0.15uf r140 100k r9 10.0k rt12 220k rcs12 165k r10 10.0k r12 10.0 r38 23.7k c66 10nf c155 680pf r155 130 r139 100k rcs11 73.2k r50 37.4 r34 100 c83 22nf r185 10.0 r154 80.6k r26 51.1k r31 11.0k rt11 220k r157 75.0 r71 4.99 r25 75.0k r40 1.0k u1 ncp81105 tsense 9 vrhot# 3 sclk 6 alert# 5 vr_rdy 8 vcc 2 en 1 sdio 4 csn3 21 csp3 20 csn1 19 csp1 18 drvon 15 pwm1 14 pwm3 13 pwm2 12 csp2 22 csn2 23 cscomp 26 ilim 27 comp 32 fb 33 vsn 35 diffout 34 vsp 36 rosc 7 vrmp 29 dgain 31 vboot 30 smod 11 od# 10 cssum 25 iout 28 csref 24 epad 37 int_sel 17 imax 16 r138 100k v_1p05_vccp od# pwm2 pwm3 pwm1 sclk sdio vr_hot vdc v5s cspp2 csn2 cspp1 csn1 smod enable alert drvon cspp3 csn3 vccu vcc_sense vss_sense vr_rdy vrmp imax vboot csn3
ncp81105, ncp81105h http://onsemi.com 7 thwn sw2 sw1 c68 22uf c217 10uf c205 10uf ca3 10uf c52 22uf c28 0.22uf c29 1uf l1 120nh mpcg0740lr12 0.7mohm + c2 33uf 1 2 c273 22uf c222 22uf c4 0.22uf c99 22uf c226 22uf c227 22uf cb3 10uf c27 1uf r121 1k c46 22uf ncp5338 u3 vin 11 vin 12 vin 13 vin 14 vswh 15 pgnd 16 pgnd 17 pgnd 18 pgnd 19 pgnd 20 vswh 31 vswh 32 vswh 33 vswh 34 vswh 35 gl 36 cgnd 37 disb# 39 pwm 40 zcd_en# 1 vcin 2 nc 3 boot 4 gh 6 phase 7 vin 9 vin 10 pgnd 21 pgnd 22 pgnd 23 pgnd 24 pgnd 25 pgnd 26 pgnd 27 pgnd 28 vswh 29 vswh 30 cgnd 5 cgnd 41 vin 42 vswh 43 vin 8 thwn 38 c176 22uf ca1 10uf c36 1uf ncp5338 u2 vin 11 vin 12 vin 13 vin 14 vswh 15 pgnd 16 pgnd 17 pgnd 18 pgnd 19 pgnd 20 vswh 31 vswh 32 vswh 33 vswh 34 vswh 35 gl 36 cgnd 37 disb# 39 pwm 40 zcd_en# 1 vcin 2 nc 3 boot 4 gh 6 phase 7 vin 9 vin 10 pgnd 21 pgnd 22 pgnd 23 pgnd 24 pgnd 25 pgnd 26 pgnd 27 pgnd 28 vswh 29 vswh 30 cgnd 5 cgnd 41 vin 42 vswh 43 vin 8 thwn 38 ca2 10uf c9 1uf c67 22uf c41 10uf c207 10uf c212 22uf c189 22uf c98 22uf c206 10uf c272 22uf c48 10uf c37 0.22uf + c3 33uf 1 2 c100 22uf c215 10uf c204 10uf c42 22uf ncp5338 u4 vin 11 vin 12 vin 13 vin 14 vswh 15 pgnd 16 pgnd 17 pgnd 18 pgnd 19 pgnd 20 vswh 31 vswh 32 vswh 33 vswh 34 vswh 35 gl 36 cgnd 37 disb# 39 pwm 40 zcd_en# 1 vcin 2 nc 3 boot 4 gh 6 phase 7 vin 9 vin 10 pgnd 21 pgnd 22 pgnd 23 pgnd 24 pgnd 25 pgnd 26 pgnd 27 pgnd 28 vswh 29 vswh 30 cgnd 5 cgnd 41 vin 42 vswh 43 vin 8 thwn 38 c43 dnp c25 1uf c184 22uf c183 22uf c5 1uf c177 22uf c45 dnp c271 22uf c31 1uf cb2 10uf c20 1uf cb1 10uf c210 22uf c78 22uf c214 10uf c190 22uf c97 dnp c216 10uf c213 22uf + c1 33uf 1 2 c32 1uf c44 1uf c95 22uf c26 1uf c196 dnp c49 10uf c84 22uf c30 1uf vdc vdc vdc v5s v5s v5s v5s thwn pwm1 vdc cspp1 csn1 pwm2 vccu cspp2 csnn2 smod vccu pwm3 drvon cspp3 csnn3 drvon vccu vccu drvon od# od# v5s locate between l1 & l2 (primary side) total vcore output capacitor: 26 x 22uf(0805) + 11 x 10uf(0805) locate in center of socket rpga989 cavity (primary side) locate in center of socket rpga989 cavity (bottom side) locate between l2 & l3 (primary side) sw3 l2 120nh mpcg0740lr12 0.7mohm l3 120nh mpcg0740lr12 0.7mohm thwn figure 5. three phase power stage circuit
ncp81105, ncp81105h http://onsemi.com 8 figure 6. two phase control circuit application vcc v5s ilim diffout rosc fb place close to l1 sclk comp diffout place close to l1 vsp csn1 imon dgain vsense int_sel cscomp r16 24.9k alert_vr 790khz switching frequency 55a maximum output current 66a current limit 1.5mohm loadline 1.7v boot voltage tsense csref cssum csn2 vr_rdy csp3 vsn sdio csp1 enable vr_hot vrmp imax vboot c82 0.01uf r31 11.0k r140 49.9k r48 100 r154 80.6k r37 1.00k c51 1nf c83 22nf c57 10pf r78 43.2 r50 37.4 r19 69.8k r139 49.9k c155 680pf r162 130 r38 23.7k u1 ncp81105 tsense 9 vrhot# 3 sclk 6 alert# 5 vr_rdy 8 vcc 2 en 1 sdio 4 csn3 21 csp3 20 csn1 19 csp1 18 drvon 15 pwm1 14 pwm3 13 pwm2 12 csp2 22 csn2 23 cscomp 26 ilim 27 comp 32 fb 33 vsn 35 diffout 34 vsp 36 rosc 7 vrmp 29 dgain 31 vboot 30 smod 11 od# 10 cssum 25 iout 28 csref 24 epad 37 int_sel 17 imax 16 r18 20.0k r25 43.2k r157 75.0 r10 10.0k c56 270pf r128 1k r26 51.1k rt12 220k r8 10.0 r185 10.0 c61 0.15uf r34 100 csn3 r43 4.75k r161 1.0k c80 22nf rcs11 73.2k c156 68pf r155 130 c66 10nf c81 1nf c79 1uf r40 1.0k rcs12 165k r156 54.9 r71 4.99 rt11 220k r9 10.0k v_1p05_vccp pwm1 od# pwm3 vr_hot vdc v5s sclk sdio csn1 smod cspp1 drvon cspp3 csn3 enable alert vss_sense vr_rdy vccu vcc_sense
ncp81105, ncp81105h http://onsemi.com 9 sw1 c67 22uf c31 1uf c9 1uf c98 22uf c177 22uf c29 1uf c5 1uf c183 22uf c28 0.22uf c84 22uf c184 22uf c49 10uf r121 1k c32 1uf c52 22uf ncp5338 u2 vin 11 vin 12 vin 13 vin 14 vswh 15 pgnd 16 pgnd 17 pgnd 18 pgnd 19 pgnd 20 vswh 31 vswh 32 vswh 33 vswh 34 vswh 35 gl 36 cgnd 37 disb# 39 pwm 40 zcd_en# 1 vcin 2 nc 3 boot 4 gh 6 phase 7 vin 9 vin 10 pgnd 21 pgnd 22 pgnd 23 pgnd 24 pgnd 25 pgnd 26 pgnd 27 pgnd 28 vswh 29 vswh 30 cgnd 5 cgnd 41 vin 42 vswh 43 vin 8 thwn 38 c204 10uf c196 22uf + c1 33uf 1 2 c215 10uf cb3 10uf c213 22uf ca3 10uf c100 22uf c212 22uf c26 1uf + c3 33uf 1 2 c227 22uf c99 22uf c205 10uf c271 22uf c226 22uf c214 10uf ca1 10uf c217 10uf c207 10uf c78 22uf l1 120nh mpcg0740lr12 0.7mohm c4 0.22uf c41 10uf c25 1uf c68 22uf c48 10uf c176 22uf cb1 10uf c272 22uf ncp5338 u4 vin 11 vin 12 vin 13 vin 14 vswh 15 pgnd 16 pgnd 17 pgnd 18 pgnd 19 pgnd 20 vswh 31 vswh 32 vswh 33 vswh 34 vswh 35 gl 36 cgnd 37 disb# 39 pwm 40 zcd_en# 1 vcin 2 nc 3 boot 4 gh 6 phase 7 vin 9 vin 10 pgnd 21 pgnd 22 pgnd 23 pgnd 24 pgnd 25 pgnd 26 pgnd 27 pgnd 28 vswh 29 vswh 30 cgnd 5 cgnd 41 vin 42 vswh 43 vin 8 thwn 38 c20 1uf c273 22uf c206 10uf c216 10uf vdc vdc v5s v5s v5s thwn thwn pwm1 cspp1 csn1 smod pwm3 cspp3 csnn3 drvon vccu drvon od# vccu l3 120nh mpcg0740lr12 0.7mohm locate between l1 & l2 (primary side) total vcore output capacitor: 20 x 22uf(0805) + 11 x 10uf(0805) locate in center of socket rpga989 cavity (primary side) locate in center of socket rpga989 cavity (bottom side) sw3 figure 7. two phase power stage circuit
ncp81105, ncp81105h http://onsemi.com 10 figure 8. single phase control circuit application vcc ilim v5s r128 1k diffout rosc fb place close to l1 sclk comp diffout place close to l1 vsp csn1 imon dgain vsense int_sel cscomp r16 24.9k alert_vr 790khz switching frequency 32a maximum output current 39a current limit 2.0mohm loadline 1.7v boot voltage tsense csref cssum vr_rdy vsn sdio csp1 enable vr_hot vrmp imax vboot c82 0.01uf r31 11.0k r140 75.0k r48 100 r154 80.6k r37 1.00k c51 1nf c57 10pf r78 43.2 r50 37.4 r19 69.8k c155 680pf r162 130 r38 23.7k u1 ncp81105 tsense 9 vrhot# 3 sclk 6 alert# 5 vr_rdy 8 vcc 2 en 1 sdio 4 csn3 21 csp3 20 csn1 19 csp1 18 drvon 15 pwm1 14 pwm3 13 pwm2 12 csp2 22 csn2 23 cscomp 26 ilim 27 comp 32 fb 33 vsn 35 diffout 34 vsp 36 rosc 7 vrmp 29 dgain 31 vboot 30 smod 11 od# 10 cssum 25 iout 28 csref 24 epad 37 int_sel 17 imax 16 r18 8.87k r25 25.5k r157 75.0 c56 270pf r26 51.1k rt12 220k r185 10.0 c61 0.15uf r34 100 csn3 r43 4.75k r161 1.0k c80 22nf rcs11 73.2k c156 68pf r155 130 c66 10nf c81 1nf c79 1uf r40 1.0k rcs12 165k r156 54.9 r71 4.99 rt11 220k r9 10.0k v_1p05_vccp pwm1 od# pwm2 pwm3 vr_hot vdc v5s sclk sdio csn1 smod cspp1 drvon enable alert vss_sense vr_rdy vccu vcc_sense
ncp81105, ncp81105h http://onsemi.com 11 sw1 c67 dnp c98 22uf c177 22uf c5 1uf c183 22uf c84 22uf c184 22uf c49 10uf r121 1k c52 dnp ncp5338 u2 vin 11 vin 12 vin 13 vin 14 vswh 15 pgnd 16 pgnd 17 pgnd 18 pgnd 19 pgnd 20 vswh 31 vswh 32 vswh 33 vswh 34 vswh 35 gl 36 cgnd 37 disb# 39 pwm 40 zcd_en# 1 vcin 2 nc 3 boot 4 gh 6 phase 7 vin 9 vin 10 pgnd 21 pgnd 22 pgnd 23 pgnd 24 pgnd 25 pgnd 26 pgnd 27 pgnd 28 vswh 29 vswh 30 cgnd 5 cgnd 41 vin 42 vswh 43 vin 8 thwn 38 c204 10uf c196 dnp + c1 33uf 1 2 c215 10uf c213 22uf c100 22uf c212 22uf c26 1uf c227 22uf c99 22uf c205 10uf c271 22uf c226 22uf c214 10uf ca1 10uf c217 10uf c207 10uf c78 22uf c4 0.22uf c41 10uf c25 1uf c68 dnp c48 10uf c176 22uf cb1 10uf c272 22uf c20 1uf c273 22uf c206 10uf c216 10uf vdc v5s v5s thwn pwm1 cspp1 csn1 smod drvon vccu locate near l1 (primary side) total vcore output capacitor: 16 x 22uf(0805) + 11 x 10uf(0805) locate in center of socket rpga989 cavity (primary side) locate in center of socket rpga989 cavity (bottom side) l1 120nh mpcg0740lr12 0.7mohm figure 9. single phase power stage circuit
ncp81105, ncp81105h http://onsemi.com 12 absolute maximum ratings electrical information ? all signals referenced to gnd unless noted otherwise. pin symbol v max v min i source i sink comp, cscomp, diffout vcc + 0.3 v ? 0.3 v 3 ma 3 ma vsn gnd + 300 mv gnd ? 300 mv vr_rdy vcc + 0.3 v ? 0.3 v n/a 5 ma vcc 6.5 v ? 0.3 v n/a n/a vrmp +25 v ? 0.3 v vr_hot#, sdio & alert# vcc + 0.3 v ? 0.3 v 0 ma 30 ma od#, smod, pwm1, pwm2, pwm3 & drvon vcc + 0.3 v ? 0.3 v 5 ma 5 ma all other pins vcc + 0.3 v ? 0.3 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. thermal information description symbol typ unit thermal characteristic qfn36 package (notes 1 and 2) r ja 68 c/w operating junction temperature range* t j ? 10 to 125 c operating ambient temperature range ? 10 to 100 c maximum storage temperature range t stg ? 40 to +150 c moisture sensitivity level msl 1 *the maximum package power dissipation must be observed. 1. jesd 51 ? 5 (1s2p direct ? attach method) with 0 lfm 2. jesd 51 ? 7 (1s2p direct ? attach method) with 0 lfm electrical characteristics (v cc = 5.0 v, v en = 2.0 v, c vcc = 0.1 f unless specified otherwise) min/max values are valid for the temperature range ? 10 c t a 100 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter symbol conditions min typ max unit vcc input supply voltage range 4.75 5.25 v quiescent current en = high; ps0, 1, 2 modes 23 29 ma en = high; ps3 mode 14 17.5 ma en = low 30 a uvlo threshold vcc rising 4.5 v vcc falling 4.0 v uvlo hysteresis 160 mv vrmp (vin monitor) uvlo threshold vrmp falling 3.0 3.2 3.4 v uvlo hysteresis 600 800 mv leakage current ps0, ps1, ps2, ps3; v vrmp = 3.2 v 70 a leakage current ps4, v vrmp = 20 v 500 na leakage current v en = 0 v, v vrmp = 20 v 500 na enable input enable high input leakage current external 1k pull ? up to 3.3 v 1.0 a
ncp81105, ncp81105h http://onsemi.com 13 electrical characteristics (v cc = 5.0 v, v en = 2.0 v, c vcc = 0.1 f unless specified otherwise) min/max values are valid for the temperature range ? 10 c t a 100 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter unit max typ min conditions symbol enable input upper threshold v upper 0.8 v lower threshold v lower 0.3 v total hysteresis v upper ? v lower 300 mv enable delay time time from enable transitioning hi to when drvon goes high. 2.4 ms sclk, sdio, alert# sclk input low voltage v ilsclk 0.45 v sclk input high voltage v ihsclk 0.66 v sdio input low voltage v ilsdio 0.42 v sdio input high voltage v ihsdio 0.72 v hysteresis voltage (sclk, sdio) v hys 100 mv output high voltage (sdio, alert#) v oh external resistive pullup to 1.05 v 1.05 v output low voltage (sdio, alert#) v ol sinking 20 ma 100 mv buffer on resistance (sdio, alert#) r on measured sinking 4 ma 5 13 leakage current pin voltage between 0 and 1.05 v ? 100 100 a pin capacitance 4.0 pf vr clock to data delay t co time between sclk rising edge and valid sdio level 4 8.3 ns setup time t su time before sclk falling (sampling) edge that sdio level must be valid 7 ns hold time t hld time after sclk falling edge that the sdio level remains valid 14 ns vr12.5 & vr12.6 dac system voltage accuracy 1.5 v dac < 2.3 v, ? 10 c t a 85 c ? 0.5 0.5 % 1.0 v dac < 1.49 v, ? 10 c t a 85 c ? 8 8 mv 0.5 v dac < 0.99 v, ? 10 c t a 85 c ? 10 10 mv dac slew rates (ncp81105) soft start slew rate svid register 2ah = default 12 mv/ s slew rate slow selectable fraction of fast slew 3 ? 24 mv/ s slew rate fast 48 mv/ s dac slew rates (ncp81105h) soft start slew rate svid register 2ah = default 2.5 mv/ s slew rate slow selectable fraction of fast slew 1 ? 5 mv/ s slew rate fast 10 mv/ s differential summing amplifier vsp input leakage current v vsp = 1.3 v 0 15 a vsn bias current ? 0.3 v v vsn 0.3 v ? 1 1 a dvid up feedforward charge ? 0.3 v v vsn 0.5 v charge per 5 mv dac increment 6.8 pc vsp input voltage range ? 0.3 3.0 v vsn input voltage range ? 0.3 0.3 v ? 3db bandwidth c l = 20 pf to gnd, r l = 10 k to gnd 10 mhz dc gain ? vsx to diffout vsp ? vsn = 0.5 v to 2.3 v 1.0 v/v
ncp81105, ncp81105h http://onsemi.com 14 electrical characteristics (v cc = 5.0 v, v en = 2.0 v, c vcc = 0.1 f unless specified otherwise) min/max values are valid for the temperature range ? 10 c t a 100 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter unit max typ min conditions symbol differential summing amplifier maximum output voltage i source = 2 ma 3.0 v minimum output voltage i sink = 2 ma 0.5 v error amplifier input bias current v fb = 1.3 v; internal integrator active ? 25 25 a open loop dc gain cl = 20 pf to gnd, rl = 10 k to gnd 80 db open loop unity gain bandwidth cl = 20 pf to gnd, rl = 10 k to gnd 20 mhz slew rate vin = 100 mv, g = ? 10 v/v, vout = 1.5 v ? 2.5 v, load = 20 pf to gnd + 10 k to gnd 20 v/ s maximum output voltage i source = 2.0 ma 3.5 v minimum output voltage i sink = 2.0 ma 1 v vr_rdy (power good) output output low saturation voltage i vr_rdy = 4 ma 0.3 v rise time 1 k external pull ? up to 3.3 v, c tot = 45 pf 100 ns fall time 1 k external pull ? up to 3.3 v, c tot = 45 pf 10 ns output voltage at power ? up vr_rdy pulled up to 5 v via 2 k 1.0 v output leakage current when high vr_rdy = 5.0 v ? 1.0 1.0 a vr_rdy delay (rising) dac = target to vr_rdy high 5.5 6 s vr_rdy delay (falling) from ocp or ovp to vr_rdy low 5 s output over voltage & under voltage protection (ovp & uvp) absolute over voltage threshold during soft ? start 2.8 2.9 3.0 v over voltage threshold above dac vsp rising 350 400 425 mv over voltage delay vsp rising to pwmx low 50 ns under voltage threshold below dac vsp falling 300 mv under ? voltage delay 5 s current balance amplifiers input bias current (after phase detection) cspx = csnx = 1.7 v ? 50 50 na common mode input voltage range cspx = csnx 0 2.3 v differential mode input voltage range csnx = 1.7 v ? 100 100 mv closed loop input offset voltage matching cspx = csnx = 1.7 v, measured from the average offset ? 1.5 1.5 mv amplifier gain 0 v < cspx ? csnx 0.1 v 5.7 6.0 6.3 v/v gain matching 10 mv cspx ? csnx 30 mv ? 3 3 % ? 3 db bandwidth 8 mhz 1 & 2 phase detection csn pin resistance to ground during phase detection only 50 k csn pin threshold voltage 4.5 v phase detect timer time from enable transitioning hi to removal of phase detect resistance 3.5 ms
ncp81105, ncp81105h http://onsemi.com 15 electrical characteristics (v cc = 5.0 v, v en = 2.0 v, c vcc = 0.1 f unless specified otherwise) min/max values are valid for the temperature range ? 10 c t a 100 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter unit max typ min conditions symbol current summing amplifier offset voltage v os v csref = 1.0 v ? 300 300 v cssum input bias current cssum = csref = 1 v ? 7.5 7.5 na csref input bias current cssum = csref = 1 v 0 4.25 a open loop gain 80 db current sense unity gain bandwidth c l = 20 pf to gnd, r l = 10 k to gnd 10 mhz max cscomp output voltage isource = 2 ma 3.5 v minimum cscomp output voltage isink = 500 a 100 mv isink = 25 a 7.0 30 mv iout output maximum output voltage r iout = 5 k 2.0 v input referred offset voltage ilim minus csref ? 1.9 1.9 mv output source current ilim sink current = 80 a 700 a current gain ai iout (iout current ) / (ilim current ); r ilim = 20 k ; r iout = 5.0 k ; v csref = 1.7 v 9.5 10 10.5 a/a dimon full scale voltage v difs 2.0 v overcurrent protection (ilim pin) 3 & 2 ? phase ps0 threshold current, 1 ? phase all ? ps threshold current delayed shutdown immediate shutdown i ds i is 9.0 13.5 10 15 11.0 16.5 a 3 ? phase, non ? ps0 threshold current delayed shutdown immediate shutdown i ds i is ps1, 2 or 3 mode (1 ? phase active) ps1, 2 or 3 mode (1 ? phase active) 4 6 a 2 ? phase, non ? ps0 threshold current delayed shutdown immediate shutdown i ds i is ps1, 2 or 3 mode (1 ? phase active) ps1, 2 or 3 mode (1 ? phase active) 6.7 10 a time for delayed shutdown 55 s oscillator maximum switching frequency see precision oscillator description 1425 khz minimum switching frequency see precision oscillator description 275 khz switching frequency tolerance ps0 mode; rrosc = 110 k 925 1025 1125 khz rosc pin output current v rosc = gnd 9.5 10 10.5 a modulators (pwm comparators) minimum pulse width 20 ns 0% duty cycle comp voltage when the pwm outputs remain lo (dual ? edge modulation only) 1.3 v 100% duty cycle comp voltage when the pwm outputs remain hi, vrmp = 12.0 v; (dual ? edge modulation only) 2.5 v pwm phase angle error between adjacent phases, 3 ? phase operation ? 20 20 deg ramp feed ? forward voltage range vrmp pin voltage 5 20 v pwm outputs (pwm1/2/3) output high voltage sourcing 500 a v cc ? 0.2 v output low voltage sinking 500 a 0.7 v
ncp81105, ncp81105h http://onsemi.com 16 electrical characteristics (v cc = 5.0 v, v en = 2.0 v, c vcc = 0.1 f unless specified otherwise) min/max values are valid for the temperature range ? 10 c t a 100 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter unit max typ min conditions symbol pwm outputs (pwm1/2/3) rise and fall times cl (pcb) = 50 pf, measured between 10% & 90% of v cc 10 ns drvon output output high voltage sourcing 500 a 3.0 v output low voltage sinking 500 a 0.1 v rise time cl (pcb) = 20 pf, vo = 10% to 90% 150 ns fall time cl (pcb) = 20 pf, vo = 90% to 10% 5 ns pwm delay time time from drvon high to first pwm 110 120 s internal pull down resistance en = low 70 k od# output output high voltage sourcing 500 a 3.0 v output low voltage sinking 500 a 0.1 v ps0 delay entering ps0; from fall of the earlier of pwm2 or pwm3 to od# rising 15 ns rise/fall time c l (pcb) = 20 pf, vo = 10% to 90% 10 ns internal pull down resistance en = low 70 k smod output output high voltage sourcing 500 a 3.0 v output low voltage sinking 500 a 0.1 v ps2/3 delay ps2&3; pwm1 rising to smod rising 10 50 ns rise/fall time c l (pcb) = 20 pf, vo = 10% to 90% 10 ns internal pull down resistance en = low 70 k vr_hot# output output low voltage i _vrhot# = ? 4 ma 0.3 v output leakage current high impedance state, v vrhot# = 3.3 v ? 1.0 1.0 a tsense input alert# assert threshold t a = 85 c 458 mv alert# de ? assert threshold t a = 85 c 476 mv vrhot# assert threshold t a = 85 c 437 mv vrhot# de ? assert threshold t a = 85 c 457 mv tsense bias current v tsense = 0.4 v, t a = 85 c 57.7 60 62.7 a vboot pin sensing current v vboot = gnd 10 a imax pin sensing current i imax v imax = gnd 9.5 10 10.5 a imax full scale voltage v imaxfs 2.0 v int_sel pin sensing current v int_sel = gnd 10 a dgain pin sensing current v dgain = gnd 10 a adc input voltage range 0 2 v
ncp81105, ncp81105h http://onsemi.com 17 electrical characteristics (v cc = 5.0 v, v en = 2.0 v, c vcc = 0.1 f unless specified otherwise) min/max values are valid for the temperature range ? 10 c t a 100 c unless noted otherwise, and are guaranteed by test, design or statistical correlation. parameter unit max typ min conditions symbol adc total unadjusted error (tue) ? 1 +1 % differential nonlinearity (dnl) 8 ? bit 1 lsb power supply sensitivity 1 % conversion time 10 s time to cycle through all inputs 250 s
ncp81105, ncp81105h http://onsemi.com 18 vr12.5 & vr12.6 vid table vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage (v) hex vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage (v) hex 0 0 0 0 0 0 0 0 off 00 0 0 1 1 1 1 1 0 1.11 3e 0 0 0 0 0 0 0 1 0.50 01 0 0 1 1 1 1 1 1 1.12 3f 0 0 0 0 0 0 1 0 0.51 02 0 1 0 0 0 0 0 0 1.13 40 0 0 0 0 0 0 1 1 0.52 03 0 1 0 0 0 0 0 1 1.14 41 0 0 0 0 0 1 0 0 0.53 04 0 1 0 0 0 0 1 0 1.15 42 0 0 0 0 0 1 0 1 0.54 05 0 1 0 0 0 0 1 1 1.16 43 0 0 0 0 0 1 1 0 0.55 06 0 1 0 0 0 1 0 0 1.17 44 0 0 0 0 0 1 1 1 0.56 07 0 1 0 0 0 1 0 1 1.18 45 0 0 0 0 1 0 0 0 0.57 08 0 1 0 0 0 1 1 0 1.19 46 0 0 0 0 1 0 0 1 0.58 09 0 1 0 0 0 1 1 1 1.20 47 0 0 0 0 1 0 1 0 0.59 0a 0 1 0 0 1 0 0 0 1.21 48 0 0 0 0 1 0 1 1 0.60 0b 0 1 0 0 1 0 0 1 1.22 49 0 0 0 0 1 1 0 0 0.61 0c 0 1 0 0 1 0 1 0 1.23 4a 0 0 0 0 1 1 0 1 0.62 0d 0 1 0 0 1 0 1 1 1.24 4b 0 0 0 0 1 1 1 0 0.63 0e 0 1 0 0 1 1 0 0 1.25 4c 0 0 0 0 1 1 1 1 0.64 0f 0 1 0 0 1 1 0 1 1.26 4d 0 0 0 1 0 0 0 0 0.65 10 0 1 0 0 1 1 1 0 1.27 4e 0 0 0 1 0 0 0 1 0.66 11 0 1 0 0 1 1 1 1 1.28 4f 0 0 0 1 0 0 1 0 0.67 12 0 1 0 1 0 0 0 0 1.29 50 0 0 0 1 0 0 1 1 0.68 13 0 1 0 1 0 0 0 1 1.30 51 0 0 0 1 0 1 0 0 0.69 14 0 1 0 1 0 0 1 0 1.31 52 0 0 0 1 0 1 0 1 0.70 15 0 1 0 1 0 0 1 1 1.32 53 0 0 0 1 0 1 1 0 0.71 16 0 1 0 1 0 1 0 0 1.33 54 0 0 0 1 0 1 1 1 0.72 17 0 1 0 1 0 1 0 1 1.34 55 0 0 0 1 1 0 0 0 0.73 18 0 1 0 1 0 1 1 0 1.35 56 0 0 0 1 1 0 0 1 0.74 19 0 1 0 1 0 1 1 1 1.36 57 0 0 0 1 1 0 1 0 0.75 1a 0 1 0 1 1 0 0 0 1.37 58 0 0 0 1 1 0 1 1 0.76 1b 0 1 0 1 1 0 0 1 1.38 59 0 0 0 1 1 1 0 0 0.77 1c 0 1 0 1 1 0 1 0 1.39 5a 0 0 0 1 1 1 0 1 0.78 1d 0 1 0 1 1 0 1 1 1.40 5b 0 0 0 1 1 1 1 0 0.79 1e 0 1 0 1 1 1 0 0 1.41 5c 0 0 0 1 1 1 1 1 0.80 1f 0 1 0 1 1 1 0 1 1.42 5d 0 0 1 0 0 0 0 0 0.81 20 0 1 0 1 1 1 1 0 1.43 5e 0 0 1 0 0 0 0 1 0.82 21 0 1 0 1 1 1 1 1 1.44 5f 0 0 1 0 0 0 1 0 0.83 22 0 1 1 0 0 0 0 0 1.45 60 0 0 1 0 0 0 1 1 0.84 23 0 1 1 0 0 0 0 1 1.46 61 0 0 1 0 0 1 0 0 0.85 24 0 1 1 0 0 0 1 0 1.47 62 0 0 1 0 0 1 0 1 0.86 25 0 1 1 0 0 0 1 1 1.48 63 0 0 1 0 0 1 1 0 0.87 26 0 1 1 0 0 1 0 0 1.49 64 0 0 1 0 0 1 1 1 0.88 27 0 1 1 0 0 1 0 1 1.50 65 0 0 1 0 1 0 0 0 0.89 28 0 1 1 0 0 1 1 0 1.51 66 0 0 1 0 1 0 0 1 0.90 29 0 1 1 0 0 1 1 1 1.52 67 0 0 1 0 1 0 1 0 0.91 2a 0 1 1 0 1 0 0 0 1.53 68 0 0 1 0 1 0 1 1 0.92 2b 0 1 1 0 1 0 0 1 1.54 69 0 0 1 0 1 1 0 0 0.93 2c 0 1 1 0 1 0 1 0 1.55 6a 0 0 1 0 1 1 0 1 0.94 2d 0 1 1 0 1 0 1 1 1.56 6b 0 0 1 0 1 1 1 0 0.95 2e 0 1 1 0 1 1 0 0 1.57 6c 0 0 1 0 1 1 1 1 0.96 2f 0 1 1 0 1 1 0 1 1.58 6d 0 0 1 1 0 0 0 0 0.97 30 0 1 1 0 1 1 1 0 1.59 6e 0 0 1 1 0 0 0 1 0.98 31 0 1 1 0 1 1 1 1 1.60 6f 0 0 1 1 0 0 1 0 0.99 32 0 1 1 1 0 0 0 0 1.61 70 0 0 1 1 0 0 1 1 1.00 33 0 1 1 1 0 0 0 1 1.62 71 0 0 1 1 0 1 0 0 1.01 34 0 1 1 1 0 0 1 0 1.63 72 0 0 1 1 0 1 0 1 1.02 35 0 1 1 1 0 0 1 1 1.64 73 0 0 1 1 0 1 1 0 1.03 36 0 1 1 1 0 1 0 0 1.65 74 0 0 1 1 0 1 1 1 1.04 37 0 1 1 1 0 1 0 1 1.66 75 0 0 1 1 1 0 0 0 1.05 38 0 1 1 1 0 1 1 0 1.67 76 0 0 1 1 1 0 0 1 1.06 39 0 1 1 1 0 1 1 1 1.68 77 0 0 1 1 1 0 1 0 1.07 3a 0 1 1 1 1 0 0 0 1.69 78 0 0 1 1 1 0 1 1 1.08 3b 0 1 1 1 1 0 0 1 1.70 79 0 0 1 1 1 1 0 0 1.09 3c 0 1 1 1 1 0 1 0 1.71 7a 0 0 1 1 1 1 0 1 1.10 3d 0 1 1 1 1 0 1 1 1.72 7b
ncp81105, ncp81105h http://onsemi.com 19 vr12.5 & vr12.6 vid table vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 vid7 hex voltage (v) vid0 vid1 vid2 vid3 vid4 vid5 vid6 0 1 1 1 1 1 0 0 1.73 7c 1 0 0 1 1 0 0 1 2.02 99 0 1 1 1 1 1 0 1 1.74 7d 1 0 0 1 1 0 1 0 2.03 9a 0 1 1 1 1 1 1 0 1.75 7e 1 0 0 1 1 0 1 1 2.04 9b 0 1 1 1 1 1 1 1 1.76 7f 1 0 0 1 1 1 0 0 2.05 9c 1 0 0 0 0 0 0 0 1.77 80 1 0 0 1 1 1 0 1 2.06 9d 1 0 0 0 0 0 0 1 1.78 81 1 0 0 1 1 1 1 0 2.07 9e 1 0 0 0 0 0 1 0 1.79 82 1 0 0 1 1 1 1 1 2.08 9f 1 0 0 0 0 0 1 1 1.80 83 1 0 1 0 0 0 0 0 2.09 a0 1 0 0 0 0 1 0 0 1.81 84 1 0 1 0 0 0 0 1 2.10 a1 1 0 0 0 0 1 0 1 1.82 85 1 0 1 0 0 0 1 0 2.11 a2 1 0 0 0 0 1 1 0 1.83 86 1 0 1 0 0 0 1 1 2.12 a3 1 0 0 0 0 1 1 1 1.84 87 1 0 1 0 0 1 0 0 2.13 a4 1 0 0 0 1 0 0 0 1.85 88 1 0 1 0 0 1 0 1 2.14 a5 1 0 0 0 1 0 0 1 1.86 89 1 0 1 0 0 1 1 0 2.15 a6 1 0 0 0 1 0 1 0 1.87 8a 1 0 1 0 0 1 1 1 2.16 a7 1 0 0 0 1 0 1 1 1.88 8b 1 0 1 0 1 0 0 0 2.17 a8 1 0 0 0 1 1 0 0 1.89 8c 1 0 1 0 1 0 0 1 2.18 a9 1 0 0 0 1 1 0 1 1.90 8d 1 0 1 0 1 0 1 0 2.19 aa 1 0 0 0 1 1 1 0 1.91 8e 1 0 1 0 1 0 1 1 2.20 ab 1 0 0 0 1 1 1 1 1.92 8f 1 0 1 0 1 1 0 0 2.21 ac 1 0 0 1 0 0 0 0 1.93 90 1 0 1 0 1 1 0 1 2.22 ad 1 0 0 1 0 0 0 1 1.94 91 1 0 1 0 1 1 1 0 2.23 ae 1 0 0 1 0 0 1 0 1.95 92 1 0 1 0 1 1 1 1 2.24 af 1 0 0 1 0 0 1 1 1.96 93 1 0 1 1 0 0 0 0 2.25 b0 1 0 0 1 0 1 0 0 1.97 94 1 0 1 1 0 0 0 1 2.26 b1 1 0 0 1 0 1 0 1 1.98 95 1 0 1 1 0 0 1 0 2.27 b2 1 0 0 1 0 1 1 0 1.99 96 1 0 1 1 0 0 1 1 2.28 b3 1 0 0 1 0 1 1 1 2.00 97 1 0 1 1 0 1 0 0 2.29 b4 1 0 0 1 1 0 0 0 2.01 98 1 0 1 1 0 1 0 1 2.30 b5 sdio sclk setup and hold times ? cpu driving sdio su t hld t vr latch figure 10. svid timing diagrams sdio sclk vr = clock to data delay in vr co_vr send t vr driving sdio, clock to data delay co_vr t
ncp81105, ncp81105h http://onsemi.com 20 state truth table state vr_rdy pin error amp comp pin ovp & uvp drvon pin smod pin od# pin method of reset vcc uvlo 0 < vcc < threshold vrmp > threshold n/a n/a n/a resistive pull down resistive pull down resistive pull down vrmp uvlo vcc > threshold 0 < vrmp < threshold n/a n/a n/a resistive pull down resistive pull down resistive pull down disabled en < threshold vcc > threshold vrmp > threshold low low disabled low low low start up delay & calibration en > threshold vcc > threshold vrmp > threshold low low disabled low low low soft start en > threshold vcc > threshold vrmp > threshold low operational active high low until first pwm1 pulse low until first pwm2 or pwm3 pulse normal operation en > threshold vcc > threshold vrmp > threshold high operational active high high in ps0 & ps1; high or may toggle in ps2 & ps3 high in ps0; low in ps1, ps2, & ps3 n/a over voltage low low dac + 400 mv high high/ toggles during output rampdown high/ toggles during output rampdown en low or cycle power under voltage low operational dac ? droop ? 300 mv high high high output voltage > dac ? droop ? 300 mv over current low operational last dac code + 400 mv low low low en low or cycle power vid code = 00h low low disabled high (pwm outputs low) low low set valid vid code
ncp81105, ncp81105h http://onsemi.com 21 controller por disable vcc > uvlo calibrate drive off phase detect soft start ramp normal vr_rdy ovp uvp en = 1 3.5 ms and cal done vccp > uvlo and dron high en = 0 vs > ovp vdrp > ilim no_cpu invalid vid vs < uvp vs > uvp dac = vid vcc < uvlo soft start ramp dac = vboot figure 11. state diagram
ncp81105, ncp81105h http://onsemi.com 22 general the ncp81105 is a single output, one ? to ? three phase, dual ? edge modulated pwm controller with a serial vid control interface designed to meet the intel vr12.5 & vr12.6 specifications. the ncp81105 implements ps0, ps1, ps2, ps3 and ps4 power states. it is designed to work in notebook and desktop cpu power supply applications. power status pwm output operating mode ps0 multi ? phase, fixed frequency, dual edge modulation (rpm modulation when optioned for single phase), inter- leaved pwm outputs (ccm mode) ps1 single ? phase (pwm1) cot (ccm mode; phases 2 & 3 disabled by od#) ps2 single ? phase (pwm1) rpm (dcm mode by smod; phases 2 & 3 disabled by od#) ps3 single ? phase (pwm1) rpm (dcm mode by smod; phases 2 & 3 disabled by od#) ps4 no switching; memory retained; svid active for 81105, the vid code change rate is controlled with the svid interface with three options as below: dvid option svid command code feature register address (contains the slew rate of vid code change) setvid_fast 01h 48 mv/ s vid code change slew rate 24h setvid_slow 02h 12 mv/ s vid code change slew rate** 25h setvid_decay 03h no control, vid code down n/a **the slow vid code change slew rate can be modified by writing to the 2ah register with the svid bus. for 81105h, the vid code change rate is controlled with the svid interface with three options as below: dvid option svid command code feature register address (contains the slew rate of vid code change) setvid_fast 01h 10 mv/ s vid code change slew rate 24h setvid_slow 02h 2.5 mv/ s vid code change slew rate** 25h setvid_decay 03h no control, vid code down n/a **the slow vid code change slew rate can be modified by writing to the 2ah register with the svid bus. serial vid the ncp81105 supports the intel serial vid (svid) interface. it communicates with the microprocessor through three wires (sclk, sdio, alert#). the table of supported registers is shown below. index name description access default 00h vendor id uniquely identifies the vr vendor. the vendor id assigned by intel to on semiconductor is 0x1ah r 1ah 01h product id uniquely identifies the vr product. the vr vendor assigns this number. r 15h 02h product revision uniquely identifies the revision or stepping of the vr control ic. the vr vendor assigns this data. r 04h 03h product date code id r 00 05h protocol id identifies the svid protocol the ncp81105 supports r 03h 06h capability informs the master of the ncp81105?s capabilities, 1 for supported, 0 for not supported bit 7: iout_format; reg 15 ffh = icc_max (=1) bit 6: adc measurement of temp; supported (= 1) bit 5: adc measurement of pin; not supported (= 0) bit 4: adc measurement of vin; supported (= 1) bit 3: adc measurement of iin; not supported (= 0) bit 2: adc measurement of pout; supported (= 1) bit 1: adc measurement of vout; supported (= 1) bit 0: adc measurement of iout; supported (= 1) r d7h 10h status_1 data register read after the alert# signal is asserted. conveying the status of the vr. r 00h
ncp81105, ncp81105h http://onsemi.com 23 index default access description name 11h status_2 data register showing optional status_2 data. r 00h 12h temp zone data register showing temperature zones the system is operating in (thermometer format with 3 degree resolution). r 00h 15h i_out 8 bit binary word adc of current. this register reads 0xff when the output current is at icc_max r 01h 16h v_out 8 bit binary word adc of output voltage, measured between vsp and vsn. lsb size is 8 mv r 01h 17h vr_temp 8 bit binary word adc of temperature. binary format in deg c, ie 100c = 64h. r 01h 18h p_out 8 bit binary word representative of output power. the output voltage is multiplied by the output current value and the result is stored in this register. r 01h 1ah v_in 8 bit binary word adc of input voltage, measured at vrmp pin. lsb size is 112 mv r 00h 1ch status 2 last read when the status 2 register is read, its contents are copied into this register. the format is the same as the status 2 register. r 00h 21h icc_max data register containing the icc_max supported by the platform. the value is measured at the imax pin upon power up and placed in this register. from that point on, the register is read only. r 00h 22h temp_max data register containing the max temperature the platform supports and the level vr_hot asserts. this value defaults to 100 c and is programmable over the svid interface r/w 64h 24h sr_fast slew rate for setvid_fast commands. binary format in mv/ s. ncp81105 ncp81105h r r 32h 0ah 25h sr_slow slew rate for setvid_slow commands. a fraction of the sr_fast rate (register 24h) determined by register 2ah. binary format in mv/ s ncp81105 ncp81105h r r 0ch 03h 26h vboot the boot voltage is programmed using a resistor on the vboot pin which is sensed on power up. the ncp81105 will ramp to vboot and hold at vboot until it receives a new svid setvid command to move to a different voltage. r 00h 2ah sr_slow selector 0001 = fast_sr/2 0010 = fast_sr/4: default 0100 = fast_sr/8 1000 = fast_sr/16 r/w 02h 2bh ps4 exit latency reflects the latency of exiting the ps4 state. the exit latency is defined as the time duration, in us, from the ack of the setvid slow/fast command to the beginning of the output voltage ramp. r 8ch 2ch ps3 exit latency reflects the latency of exiting the ps3 state. the exit latency is defined as the time duration, in us, from the ack of the setvid slow/fast command until the ncp81105 is capable of supplying max current of the commanded ps state. r 55h 2dh enable to ready for svid time reflects the latency from enable assertion to the vr controller being ready to accept an svid command. the latency is defined as the time duration, in s: (x/16)*2 y . x = bits [3:0]: 4 bit value 0000 to 1111 y = bits [7:4]: 4 bit value 0000 to 1111 r cah 30h vout_max programmed by master and sets the maximum vid the vr will support. if a higher vid code is received, the vr will respond with a ?not supported? acknowledgement. vr12.5 & vr12.6 vid format, e.g., b5h = 2.3 v (see vid table) rw b5h 31h vid setting data register containing currently programmed vid voltage. vid data format. vr12.5 & vr12.6 vid format, e.g., 97h = 2.0 v rw 00h 32h pwr state register containing the current programmed power state. rw 00h
ncp81105, ncp81105h http://onsemi.com 24 index default access description name 33h offset sets offset in vid steps added to the vid setting for voltage margining. bit 7 is sign bit, 0 = positive margin, 1 = negative margin. remaining 7 bits are # vid steps for margin 2s complement. 00h=no margin 01h=+1 vid step 02h=+2 vid steps ffh= ? 1 vid step feh= ? 2 vid steps. rw 00h 34h multivr config bit 0 set to 1 causes vr_rdy to respond to a setvid (0.0 v) command as a valid vid voltage setting instead of a disable command (only after ramping to a non ? zero vid after startup). bit 1 set to 1 locks the current vid and power state settings until such time as the vr is issued a setps(00h) command. rw 00h
ncp81105, ncp81105h http://onsemi.com 25 phase detection sequence during start ? up, the number of operational phases is determined by the internal circuitry monitoring the csn inputs. normally, ncp81105 operates as a 3 ? phase pwm controller. connecting the csn2 pin to v cc programs 2 ? phase operation using phases 1 and 3. connecting the csn3 pin to v cc programs 1 ? phase operation using phase 1. prior to soft start, while enable is high, the csn2 and csn3 pins have approximately 50 k to ground. an internal comparator checks the voltage of the csn pins and compares them to a reference voltage. if either pin is tied to v cc , its voltage is above the reference voltage and the controller is configured for reduced ? phase operation. otherwise, the resistance pulls the pin voltages to ground, which is below the reference, and the part operates in 3 phase mode. phase count table number of phases programming pins (csnx) what to do with unused pins 3 all csn pins connected normally no unused pins 2 tie csn2 to vcc through 2 k ; csn3, csn1 connected normally tie csp2 to ground; float pwm2 1 tie csn3 to vcc through 2 k ; csn1 connected normally tie csn2, csp2 & csp3 to ground; float pwm2, pwm3 & od# boot voltage programming the ncp81105 has a vboot voltage register that can be externally programmed. the boot voltage for the ncp81105 is set using the vboot pin on power up. a 10 a current is sourced from the vboot pin into an external resistance connected to ground, and the resulting voltage is measured. this is compared with the thresholds in the table below and the corresponding value is placed in the vboot register (26h). this value is set on power up and cannot be changed after the initial power up sequence is complete. boot voltage table resistance boot voltage 30.1k 0 v 49.9k 1.65 v 69.8k 1.70 v open 1.75 v addressing the ncp81105 the ncp81105 has fixed svid device address 0000. remote sense amplifier a high performance, high input impedance, differential amplifier is provided to accurately sense the output voltage of the regulator. the vsp and vsn inputs should be connected to the regulator?s output voltage sense points. the remote sense amplifier takes the difference of the output voltage with the dac voltage and adds the droop voltage and a voltage to bias the output above ground. v diffout v vsp v vsn 1.3 v v dac v droop v csref v droop v cscomp droop gain scaling (see the droop gain table)
ncp81105, ncp81105h http://onsemi.com 26 high performance voltage error amplifier the remote sense amplifier output is applied to a type 3 compensation network formed by the error amplifier, external tuning components, and internal integrator. the non ? inverting input of the error amplifier is connected to the same reference voltage used to bias the remote sense amplifier output. the integrating function of the type 3 feedback compensation is performed internally and does not require external capacitor cf1 (see below). vbias error comp cf1 cin cf rin2 rin1 rf _ + figure 12. traditional type 3 external compensation vbias error comp cin cf rin2 rin1 rf _ + figure 13. ncp81105 modified type 3 external compensation initial tuning should be based on traditional type 3 compensation. when ideal type 3 component values have been determined, the closest setting for the internal integrator is given by the following equation: int_setting 4.83 10 ? 12 rf rin1 cf1; rf&rin1inohms, cf1innf the internal integrator is programmed using the int_sel pin according to the following table: integrator table r int_sel int_setting 10k 1 22k 2 36k 4 51k 8 68k 10 91k 12 120k 16 160k 32 220k 64 recalculation of the initial tuning should be performed using the cf1 value given by the cf1 equation below in order to determine whether readjustment of other components would provide more optimal compensation. cf1 (nf) 2.07 10 5 int_setting (rf rin1) if an acceptable tuning cannot be produced by the closest equivalent type 3 cf1, then re ? optimization should be tried with a different internal integrator setting.
ncp81105, ncp81105h http://onsemi.com 27 differential current balance amplifiers each phase has a low offset differential amplifier to sense the current of that phase in order to balance current. the csnx and cspx pins are high impedance inputs, but it is recommended that the external filter resistor rcsn not exceed 10 k to avoid of fset due to leakage current. it is also recommended that the voltage sense element be no less than 0.5 m for best current balance. the external filter rcsn and ccsn time constant should match the inductor l/dcr time constant, but fine tuning of this time constant is not required. ccsn rcsn dcr lphase 1 2 swnx vout cspx csnx r csn l phase c csn * dcr figure 14. the individual phase current signals are combined with the comp and ramp signals at each pwm comparator input. in this way, current is balanced via a current mode control approach. total current sense amplifier the ncp81105 uses a patented approach to sum the phase currents into a single, temperature compensated, total current signal. this signal is then used to produce the output voltage droop, monitor total output current, and shut off switching if current exceeds the set limit. the rref resistors average the voltages at the output sides of the inductors to create a low impedance reference voltage at csref. the rph resistors sum currents from the switchnodes to the virtual csref potential created at the cssum pin by the amplifier. the total current signal at the amplifier output is the difference between cscomp and csref. the amplifier lowpass filters and amplifies the voltage across the inductors to extract only the voltage across the inductor series resistanc es (dcr). cscomp cssum csref rcs2 csn2 csn1 swn1 swn2 csn3 swn3 rref2 rref1 rref3 rph1 rph2 rph3 rcs1 ccs1 ccs2 rth cref figure 15. the equation for the dc total current signal is: v cscomp ? csref ? rcs2 rcs1*rth rcs1 rth rph * iout total * dcr set the dc gain by adjusting the value of the rph resistors to make the ratio of total current signal to output current equal to the desired loadline. the rph resistor value must be high enough to keep rph current below 0.5 ma when switchnodes are at nominal input voltage. if the voltage from cscomp to csref at iccmax is less than 100 mv, increase the gain of the cscomp amp by a multiple of 2 until it is at or above 100 mv, and insert the resistor between the dgain pin and ground that results in the correct loadline. see the droop gain table. this is recommended to provide a high enough total current signal to avoid impacts of offset voltage on current monitoring and the overcurrent shutdown threshold.
ncp81105, ncp81105h http://onsemi.com 28 an ntc thermistor (rth) in the feedback network placed near the phase 1 inductor senses the inductor temperature and compensates both the dc gain and the filter time constant for the dcr change with temperature. the values of rcs1 and rcs2 are set based on the effect of temperature on both the thermistor and inductor. the thermistor should be placed near the phase 1 inductor so that it measures the temperature of the inductor providing current in the ps1 power mode. the pole frequency (f p ) of the cscomp filter should be set equal to the zero frequency (f z ) of the output inductor. this causes the total current signal to contain only the component of inductor voltage caused by the dcr voltage, and therefore to be proportional to inductor current. connecting ccs2 in parallel with ccs1 allows fine tuning of the pole frequency using commonly available capacitor values. it is best to perform fine tuning during transient testing. f z dcr@25 c 2*pi*l phase f p 1 2 * pi * rcs2 rcs1*rth@25 c rcs1 rth@25 c * ( ccs1 ccs2 ) programming the loadline (droop gain) an output loadline is a power supply characteristic wherein the regulated (dc) output voltage decreases proportional to load current. this characteristic reduces the amount of output capacitance needed to minimize output voltage variation during load transients that exceed the speed of the regulation loop. in the ncp81105, a loadline is produced by adding a signal proportional to output load current to the output voltage feedback signal ? thereby satisfying the voltage regulator at an output voltage reduced in proportion to load current. the loadline is programmed by the combined gains of the total current sense amplifier and the gain from the output of this amplifier to the input of the remote sense amplifier. the latter gain is referred to as droop gain scaling, and has four possible values programmed by the value of resistance connected from the dgain pin to ground. for systems with full load output voltage droop greater than 100 mv, the droop gain scaling can be 100%. other systems should use lower droop gain scaling and correspondingly higher total current sense amplifier gain, such that at full load the cscomp to csref voltage is 100 mv or greater. the following table shows the dgain resistances required to program different droop scalings. droop gain table r dgain droop gain scaling effect 10k 100% droop equals the cscomp to csref voltage 25k 50% droop equals half of the cscomp to csref voltage 45k 25% droop equals one quarter of the cscomp to csref voltage 70k 0% zero milliohm loadline (no loadline) programming the current limit the current limit thresholds are programmed with a resistor between the ilim and cscomp pins. the ilim pin voltage is a buffered replica of the csref voltage. the ilim current is mirrored internally to the current limit comparators and to iou t (increased by the iout current gain). the 100% current limit trips if ilim current exceeds the delayed shutdown threshold for the delayed shutdown time. current limit trips with minimal delay if ilim current exceeds the immediate shutdown threshold. set the value of the current limit resistor based on the cscomp ? csref voltage as shown below. r limit rcs2 rcs1*rth rcs1 rth rph * iout limit * dcr i ds or r limit v cscomp ? csref@ilimit i ds
ncp81105, ncp81105h http://onsemi.com 29 cscomp cssum csref _ + rcs2 csn2 csn1 swn1 swn2 csn3 swn3 rref2 rref1 rref3 rph1 rph2 rph3 rcs1 ccs1 ccs2 rth cref riout rilim ilim buffer iout to remote sense amplifier controller comparators current limit scaling rdgain dgain mirror current figure 16. programming iout the iout pin sources a current equal to the ilim current gained by the iout current gain. the voltage on the iout pin is monitored by the internal a/d converter and should be scaled with an external resistor to ground such that a load equal to iccmax generates a 2 v signal on iout. a pull ? up resistor to 5 v v cc can be used to offset the iout signal positive if needed. r iout v dimax *r limit ai iout *
r cs2 r cs1 *rth r cs1 rth rph
*iout icc_max * dcr programming icc_max the svid interface conveys the platform icc_max value to the cpu from register 21h. a resistor to ground on the imax pin programs this register at the time the part in enabled. current is sourced from this pin to generate a voltage on the program resistor. the value of the register is 1 a per lsb and is set by the equation below. the resistor value should be no less than 10k. icc_max 21h r*i imax * 256 a v imaxfs improving dynamic vid (dvid) settling time upon each increment of the internal dac following a dvid up command, the ncp81105 outputs a pulse of current from the vsn pin. if a parallel rc network is inserted into the path from vsn to vss_sense, the voltage between vsp and vsn is temporarily decreased, which causes the output voltage during dvid to be regulated slightly higher to compensate for the response of the droop function to output current flowing into the output capacitors.
ncp81105, ncp81105h http://onsemi.com 30 vsp vsn _ + vss_sense vcc_sense rff cff dvid up controller amplifier remote sense dac increment _ + vsn dac current pulses figure 17. the r and c values should be chosen according to the following equations: r ff loadline * cout 1.35 * 10 ? 9 c ff 200 r ff nf programming tsense a temperature sense input is provided. a precision current is sourced out the output of the tsense pin to generate a voltage on the temperature sense network. the voltage on the temperature sense input is sampled by the internal a/d converter and then digitally converted to temperature and stored in svid register 17h. a 220k ntc similar to the murata ncp15wm224e03rc should be used. precision oscillator a programmable precision oscillator is provided to control the switching frequency of each phase. the oscillator serves as the master clock to the ramp generator circuits, which each run at the same frequency. the rosc pin sources a current into an external programming resistor. the voltage present at the rosc pin is read by the internal adc and used to set the frequency according to the following table.
ncp81105, ncp81105h http://onsemi.com 31 switching frequency table (ps0) rosc (k ) frequency (khz) rosc (k ) frequency (khz) rosc (k ) frequency (khz) rosc (k ) frequency (khz) 10 246 37.4 445 75 656 127 1132 13.3 272 42.2 468 80.6 720 133 1185 16.2 298 46.4 492 86.6 785 143 1236 19.6 323 49.9 515 93.1 845 150 1285 23.2 348 54.9 538 100 906 162 1333 26.1 373 60.4 561 105 966 169 1377 29.4 397 64.9 584 113 1023 187 1426 33.2 421 69.8 605 121 1078 210 1475 ramp generator circuits in ps0, the oscillator controls the frequency of triangle ramps for the pulse width modulator. ramp amplitude depends on the vrmp pin voltage in order to provide input voltage feed forward compensation. the ramps have equal phase displacement with respect to each other. ramp feed ? forward circuit and ramp uvlo the ramp generator includes voltage feed ? forward control that varies the ramp magnitude proportional to the vrmp pin voltage. the pwm ramp voltage is changed according to the following: vin comp ? il duty vramp_pp v ramppk pkpp 0.1 * v vrmp the vrmp pin also has a uvlo function. the vrmp uvlo is only active after the controller is enabled. the vrmp pin is a high impedance input when the controller is disabled or put into ps4. the resistance of an rc filter at the vrmp pin shoul d not exceed 10 k . pwm comparators the noninverting input of each comparator (one for each phase) is connected to the summation of the output of the error amplifier (comp) and each phase current (i l * dcr * phase balance gain factor). the inverting input is connected to the triangle ramp voltage of that phase. the output of the comparator generates the pwm output. during steady state ps0 operation, the main rail pwm pulses are centered on the valley of the triangle ramp waveforms and both edges of the pwm signals are modulated. during a transient event, the duty cycle can increase rapidly as the error amp signal increases with respect to the ramps, to provide a highly linear and proportional response to the step load. power state 1 (ps1) the ncp81105 supports ps1 by providing the od# output. when the od# output is connected to the phase 2 and 3 drmos zcd inputs, the ps1 state causes the ncp81105 to send low levels on od#, pwm2 and pwm3, causing the power stages of phases 2 and 3 to be tri ? stated (both high and low side fets off). the modulation mode changes from constant ? frequency dual ? edge modulation to constant on time modulation.
ncp81105, ncp81105h http://onsemi.com 32 ps1 pwm1 smod drvl1 od# 0 current drvh1 ? sw1 inductor ps0 ps2 ph1 (pwm2 & pwm3 low) (pwm2 & pwm3 active) (pwm2 & pwm3 low) ps0 ps1 (pwm2 & pwm3 low) (pwm2 & pwm3 active) average phase current figure 18. zero cross detect (zcd) enabling (ps2) the ncp81105 supports the drmos zcd function (diode emulation) by providing the smod output. when the controller receives an svid command asking for ps2 mode (lighter load current condition), pwm2, pwm3 and od# are held low, causing the power stages of phases 2 and 3 to be inactive (open circuit). when the ncp81105 detects that inductor current is no longer positive, smod is pulled low to enable the drmos diode emulation function, and the pwm1 output continues full ? range two ? state outputs (from 0 v to the v cc rail). for drmos without a zcd function, when smod goes low in response to the ncp81105 detecting that inductor current is no longer positive, drmos synchronous rectification is immediately disabled. for ps0 and ps1 states, smod stays high, disabling the drmos zcd function. protection features input under voltage protection ncp81105 monitors the vcc supply voltage at the vcc pin and the vdc power source at the vrmp pin in order to provide under voltage protection. if either supply dips below their threshold, the controller will shut down the outputs. upon recovery of the supplies, the controller reenters its startup sequence, and soft start begins. soft start soft start is implemented internally. a digital counter steps the dac up from zero to the target voltage based on the predetermined slew rate in the spec table. the csn2 and csn3 pins will start out applying a test resistance to collect data on phase count. after the configuration data is collected, the controller is enabled and sets the od# and smod signals low to force the drivers to stay in diode mode. drvon will then be asserted to enable the drivers. a period of time after the controller sen ses that dr von is high, the comp pin is released to begin soft ? start. the dac ramps from zero to the target dac code and the pwm outputs will begin to fire. smod will go high when the first pwm1 pulse is produced to preclude discharge of a pre ? charged output. upon pwm2 or pwm3 going high for the first time, od# is set high.
ncp81105, ncp81105h http://onsemi.com 33 soft ? start sequence en vcc drmos enabled smod dron od# pwm1 vout pwm2 comp dac softstart delay t a figure 19. over current latch ? off protection the ncp81105 provides two different types of current limit protection. during normal operation a programmable total current limit is provided that is scaled back during reduced ? phase, power saving operation. this limit is programmed with a resistor between the cscomp and ilim pins. the current from the ilim pin to this resistor is then compared to internal i ds and i is currents. if the ilim pin current exceeds the i ds level, an internal latch ? off timer starts. when the timer expires, the controller shuts down if the fault is not removed. if the current into the pin exceeds i is , the controller will shut down immediately. to recover from an ocp fault, the en pin must be cycled low. the over ? current limit is programmed by a resistor from the ilim pin to the cscomp pin. the resistor value can be calculated by the following equation: r ilim v cscomp v csref i ds output under voltage monitor the output voltage is monitored by a dedicated dif ferential amplifier. if the output falls below target by more than the ?under voltage threshold below dac ? droop?, the uvl comparator sends the vr_rdy signal low. over voltage protection during normal operation the output voltage is monitored at the differential inputs vsp and vsn. if the output voltage exceeds the dac voltage by the ?over voltage threshold above dac?, pwms will be forced low, and the smod pin will also go low when the voltage drops below that threshold. after the ovp trip the dac will ramp slowly down to zero to avoid a negative output voltage spike during shutdown. if the dac + ovp threshold drops below the output, smod will again go high, and will toggle between low and high as the output voltage follows the dac + ovp threshold down. when the dac gets to zero, the pwms will be held low and the smod and drvon pin voltages will remain high. to reset the part, the en pin must be cycled low. during soft ? start, the ovp threshold is set to the absolute over voltage threshold. this allows the controller to start up without false triggering the ovp if residual voltage from a prior period of operation is already present at the output.
ncp81105, ncp81105h http://onsemi.com 34 ovp threshold behavior ? normal ps0 and ps1 operation dac smod pwm triggered ovp latch off vsp ? vsn od# fault (vsp short to ground) latched rampdown dac dac smod pwm triggered ovp latch off vsp ? vsn od# fault (vsp short to ground) latched rampdown dac ps0 ps1 figure 20. ovp threshold behaviour during soft ? start into pre ? charged output figure 21. dac ovp threshold during soft ? start smod pwm vsp ? vsn (precharged) od# ovp threshold after soft ? start 0 reached target vid
ncp81105, ncp81105h http://onsemi.com 35 printed circuit board layout notes the ncp81105 has differential voltage and current monitoring. this improves signal integrity and reduces noise issues related to layout for easy design use. to ensure proper function there are some general pcb layout rules to follow: careful layout for per ? phase and total current sensing are critical for jitter minimization, accurate current balancing and limiting, and iout reporting. give the first priority in component placement and trace routing to per phase and total current sensing circuits. the per phase inductor current sense rc filters should always be placed as close to the csn and csp pins on the controller as possible. the filter cap from cscomp to cssum should also be close to the controller. the temperature compensating thermistor should be placed as close as possible to the phase 1 inductor. the wiring path between rcs2 and rphx should be kept as short as possible and well away from switch node lines. the above layout notes are shown in the following diagram: controller switchnode csref 40 cssum 42 cscomp 43 csp1 34 csn1 35 terminal to inductor as possible to place as close per phase current sense close to cspx pins rc should be placed _ + _ + _ + rref2 ccs1 rph1 rph2 rref1 rcsp1 rcs2 ccs2 ccsp1 csp2 38 csn2 39 rcsp2 ccsp2 phase 1 inductor vout terminal to inductor from switchnode lines rcs1 rth keep this path as short as possible, and well away switchnode terminal to inductor vout terminal to inductor figure 22. place the v cc decoupling caps as close as possible to the controller vcc pin. for any rc filter on the vcc pin, the resistor should be no higher than 5 to prevent large voltage drop. the small feedback cap from comp to fb should be as close to the controller as possible. keep the fb traces short to minimize their capacitance to ground. ordering information device package shipping ? ncp81105mntxg qfn36 (pb ? free) 5000 / tape & reel NCP81105HMNTXG qfn36 (pb ? free) 5000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp81105, ncp81105h http://onsemi.com 36 package dimensions qfn36 5x5, 0.4p case 485cc issue o seating note 4 k 0.15 c (a3) a a1 d2 b 1 10 19 36 e2 36x l 36x bottom view top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c e plane note 3 l1 detail a l alternate constructions l a 0.10 b c 0.05 c a 0.10 b c m m m soldering footprint* dimensions: millimeters 3.64 5.30 5.30 0.40 0.63 0.25 36x 36x pitch pkg outline 1 3.64 recommended notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimensions: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. dim min max millimeters a 0.80 1.00 a1 ??? 0.05 a3 0.20 ref b 0.15 0.25 d 5.00 bsc d2 3.40 3.60 e 5.00 bsc 3.60 e2 3.40 e 0.40 bsc l 0.30 0.50 l1 ??? 0.15 k 0.35 ref a 0.10 b c m *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp81105/d intel is a registered trademark of intel corporation in the u.s. and/or other countries. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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